הלינקייה: מגזין חודשי למפתחים

רוצה לשמוע על כל האירועים, המדריכים, הקורסים והמאמרים שנכתבו החודש ?
הלינקייה הינו מגזין חופשי בעברית שמשאיר אותך בעניינים.
בלי ספאם. בלי שטויות. פעם בחודש אצלך בתיבה.

Automatic Variables

The GNU make lets us interact with it using makefile variables. Using automatic variables, we can shorten our makefiles and avoid repetitions, by using the data make has at hand when running the build process. Before we get to the examples, I'd like to list the automatic variables most widely used in makefiles.

$@ - The filename of the target

$< - The filename of the first prerequisite

$? - The names of the prerequisites that are newer than the target

$^ - The filenames of all prerequisites

And here are some more automatic variables which will be used and discussed later on the course

$* - The Stem of the file

$+ - A list of all prerequisite filenames (with duplicates)

$% -The filename element of an archive member specification.

objects = source1.o source2.o source3.o
target = runme
RM = rm -f
 
$(target): $(objects)
	@echo "Building Executable $@"
	@cc $^ -o $@
 
source1.o: source1.c 
	@cc -c $<
 
source2.o: source2.c 
	@cc -c $<
 
source3.o: source3.c 
	@cc -c $<
 
clean:
	@echo "Cleaning Up"
	@$(RM) $(target) $(objects)

This second example uses a perl script to generate the executable.

hello: main.o
        $(CC) $^ -o $@
 
main.o: main.c
        $(CC) -c main.c
 
main.c: main.template
        perl prepare_source.pl $< > $@
 
clean:
        rm hello *.o
##########################
# The .SILENT special target 
# saves us the trouble of prefixing 
# every command with a @. 
# Every target marked SILENT will not echo
# its output
 
.SILENT: debug
 
SOURCES = *.c
 
debug: $(SOURCES)
        echo "A source file has changed: $?"
        touch debug
 
course: